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STEL-9244 Data Sheet
STEL-9244
5 - 40 MHz QPSK Burst Receiver
R
Key Features
s Burst QPSK demodulation s Data rate is 2.56 Mbps s Tunable 5 - 40 MHz RF input frequency for system flexibility s Fast acquisition time to minimize channel overhead; short preamble & short guard time between bursts s MAC friendly features (see Page 9)
Easy-to-Implement Solution to the Upstream Demodulation Challenge
Stanford Telecom's burst QPSK demodulator products provide the fastest, easiest way to design complete headend QPSK receivers. The STEL-9244 offers a ready-made solution to one of the most difficult technical challenges in implementing interactive broadband services -providing the upstream demodulation functions which enable information transmitted by subscribers to be received by the headend equipment. As a companion product, the STEL-1108 provides QPSK modulation from a set-top box or cable modem.
presence of impulse noise and provides stable, repeatable performance. The unit is tunable to receive TDMA and FDMA signals over a broad input frequency range of 5 - 40 MHz. QPSK (Quaternary Phase Shift Keying) has been shown to be robust and reliable in field proven tests and is an emerging industry standard for the upstream channel.
Ideal for High Speed Data, Voice, and Video Upstream Applications
Data bit length per burst is programmable by the user for compatibility with ATM and other packet lengths. The bit rate is 2.56 Mbps for optimal T1 data and telephony performance.
High Performance for Efficient Utilization of Upstream Spectrum
The STEL-9244 delivers extremely fast acquisition times to minimize channel overhead. Our digital approach, using differential encoding and coherent detection, results in robust performance in the
Compact Form Factor
The unit measures 4.5" x 5.5" x .5", which makes it an ideal size for mounting as a daughter card.
PRELIMINARY PRODUCT INFORMATION
2
STEL-9244
Functional Description
The STEL-9244 (STEL-9244A for the final version using a custom ASIC in place of the two Altera FPGAs) is a burst QPSK receiver designed for fast acquisition of closely spaced TDMA burst signals. Figure 1 below is a simplified block diagram.
Operation
The unit is initially configured using the Serial Control input to the Microprocessor. After the input frequency is programmed, the desired signal will be tuned to 70 MHz for digitization and processing. The input signal consists of a 14 symbol preamble followed by the data packet. The packet length may be programmed. When the input signal is demodulated, the data bits are framed by the DATAVAL signal. An average of the input signal and input noise power is available on the RSSI bus.
70 MHz 5 - 40 MHz Tuner
DATAVAL DATA CLK
Serial Control RESET +5V +12V GND
Microprocesor
Digital Demod
RSSI Bus RSSIVAL RSSI TYPE RSSIEN
Figure 1 - Receiver Block Diagram
Specifications
Input Characteristics
Frequency Range Input Signal Level Input Noise Level Minimum Eb/No Input Impedance Max Input Power PLL Tuning Time 5 to 40 MHz > -5 dBmV < -10 dBmV 9 dB for input > -3 dBmV 13 dB for input < -3 dBmV 75 Ohms -20 dBm Approx. 30 ms 1.28 Msps x 0.6% = 7.68 kHz
Master Clock Input (option)
Frequency Stability Duty Cycle 43.52 MHz 25 ppm 45/55
Temperature Range
Operational Storage 0 to 70 C -40 to +85 C
Input Freq. Accuracy Symbol Rate x 0.6% = Performance
BER Guard Time Preamble Data Rate Burst Length Retune Rate 5 x 10-6 max. for Eb/No=13 dB @ signal input level = +5 dBmV 2 symbols min. 1111110000 110000000000000000 (14 symbols = 28 bits) 2.56 Mbps QPSK (differentially encoded) Up to 2K bytes* Up to 25 command strings/second
Supply Voltages
Digital Analog +5 V @ 850 mA typ. +12 V @ 280 mA typ.
*Long burst lengths may require precision Tx bit clk or locked Tx & Rx clocks (See Fig. 2).
STEL-9244
3
PRELIMINARY PRODUCT INFORMATION
Packet Length Considerations
The maximum packet length is determined by the transmitter bit clock accuracy. Since the STEL-9244 performs a one-time bit synchronization during the preamble, the bit timing accuracy will degrade as the transmitted bit timing drifts with respect to the STEL-9244's bit clock. This can cause the BER per-
formance to degrade near the end of the packet when long packets are transmitted. Figure 2 shows the transmit bit clock accuracy requirements vs. packet length. This effect can be eliminated by frequency locking the receiver's time base to the transmitter's time base.
Transmitter
Figure 2
Tx Filter Coefficients
The receiver works well with a transmit spectrum designed for alpha = 0.4, root raised cosine. The following recommended transmit FIR filter coefficients (Set A) are as calculated in the STEL-1208, the STEL-1108 evaluation board. The FIR filter coefficients (Set B) form a specially shaped/matched filter for use with the STEL-9244. Set B may improve the Bit Error Rate performance by approximately 0.5 dB, compared to Set A, when using the STEL-1108 as the modulator.
Set A
FIR Filter Coefficients 0, 31 1, 31 2, 29 3, 28
0
4, 27 5, 26 6, 25 7, 24
-5
8, 23 9, 22 10, 21 11, 20
8
12, 19 13, 18 14, 17 15, 16
7
3
-2
-15
99
3
7
-41
203
-2
15
-41
272
Set B
FIR Filter Coefficients 0, 31 1, 31 2, 29 3, 28
0
4, 27 5, 26 6, 25 7, 24
-14
8, 23 9, 22 10, 21 11, 20
29
12, 19 13, 18 14, 17 15, 16
-36
6
-7
-25
139
5
17
-93
346
-5
39
-114
485
WCP 52121.c-8/19/96
PRELIMINARY PRODUCT INFORMATION
4
STEL-9244
Input Level Dynamic Range
The input level dynamic range of the receiver is a function of Eb/No, as shown in Figure 3. In a typical dataover-CATV system, as the transmit level is increased, the Eb/No will increase, and the burst receiver will continue proper reception for over a 30 dB range. Figure 3 shows the typical operational area of an STEL9244 board. It shows that the best operating condition requires greater than 0 dBmV input signal level and less than -10 dBmV noise level. Note: In general, higher input signal is required when S/N ratio is low. The S/N ratio can be obtained from the chart by subtracting signal level from the noise level. The Eb/No can be calculated by subtracting 3 dB from the S/N ratio (for QPSK).
Adaptive Threshold Function
In order for the adaptive threshold function to operate correctly, an occasional measurement of the background channel noise must be made by the STEL-9244. The measurement period is equal to the user-programmed Noise Accumulator Length (Serial Byte #13). This should be left at the factory setting of 191 symbols. The measurement need only be performed frequently enough to allow the receiver to track the average background channel noise level (on the order of minutes).
Burst Demod Dynamic Range
30 25 20
Signal Level (dBmV)
Operational Area Signal Compression
15
Legend: Excess Noise
10 5 0 -5
BER Rate
= 1e-4 = 1e-5 = 1e-6 = 1e-7 = 1e-8 = 1e-9
Too Little Signal
-10 -60
-50
-40
-30
-20
-10
-7
0
Noise Level (dBmV in Symbol Rate BW)
WCP 52504.c-12/10/96
Figure 3. Burst Demod Dynamic Range (Typical)
STEL-9244
5
PRELIMINARY PRODUCT INFORMATION
Command Strings
The unit is controlled via a serial TTL interface, using industry standard UART timing, having the following parameters: 19.2 K baud, 1 start bit, 8 data bits, 1 stop bit, no parity. The unit can accept up to 25 command strings per second. A command string consists of bytes 1 through n for n = 1 . . . 19. Download command software is also included in the STEL-9244 shipping package that can be used to configure the unit. Note that "not" all bytes must be sent in order to configure the unit. Normally, only the first five (5) command bytes need to be sent, overwriting the default values. See the following example. A recommended STEL-9244 test fixture design is provided, Figure 6, to simplify I/O interface connection.
Serial Configuration Example
To configure the STEL-9244 for 10 MHz input and 60 byte packet length, send: 04, F4, 01, 10, FF Byte 1 04: 4 command bytes follow (stream length)
Byte 2,3 F4,01: (10 MHz-5 MHz)/10 kHz = 500 (decimal) = 01, F4 (hex) Byte 4,5 10,FF: 60 byte x (4 symbols/byte) = 240 symbols (decimal) = F0 (hex) Value = 10000 (hex) - F0 (hex) = FF, 10 (hex) The remaining configuration values are factory pre-set for optimal performance.
Description Default Setting (Hex)
Byte # 1 2 3 4 5 6 7 8 9 10 11
Value 2 0F 00-FF (LSB) 00-0F (MSB)
Number of command bytes following. Tuning steps in 10 kHz increments from 5 MHz. Default = 10 MHz F4 01 00 FE 00 00 80 00 F0 00
00-FF (LSB) 16 Bit number specifying packet length "A" in symbols. 00-FF (MSB) Value = 10000 hex - "Packet Length" hex 0/1 00-FF Spectral Inversion, 0 = default (not enabled) Threshold Gain: Sets ratio of detection threshold to noise average. This determines the false detection vs. missed detection performance. (not enabled)
00-FF (LSB) Threshold Lower Limit: Sets minimum adaptive threshold value. Prevents 00-FF (MSB) threshold from falling too low, causing excessive false detects. Threshold Upper Limit: Sets maximum adaptive threshold value. Prevents 00-FF (LSB) threshold from rising too high, causing missed detects. Setting upper 00-FF (MSB) threshold equal to lower threshold results in a fixed threshold. Signal Accumulator Length: Sets number of symbols over which accumulator averages signal power. Default=191 symbols. (Length=256-programmed byte) Changing this default will necessitate recalibration of the signal RSSI table (Table 1). Noise Accumulator Length: Number of symbols over which accumulator averages noise power. Default=191 symbols. (Length=256-programmed byte) (Do not change) Threshold Offset (not enabled) RSSI View Port Byte: upper 4 bits = signal; lower 4 bits = noise
12
00-FF
40
13 14 15 16 17 18 19 20
00-FF 00-FF 00-88
40 00 51 00 FE 0C FF FF
00-FF (LSB) 16 Bit number specifying packet length "B" in symbols. 00-FF (MSB) Value = 10000 hex - "Packet Length" hex 00-0E 00-FF 00-FF Unique Word Detect Qualifier: Number of zeroes out of 14 to search for in preamble. RSSI Noise Holdoff Value: 16 bit number specifying number of symbols to wait before taking a second RSSI noise measurement. Value = FFFF hex - number of symbols.
PRELIMINARY PRODUCT INFORMATION
6
STEL-9244
RSSI
The received signal strength output bus gives signal power as an 8 bit number. This function supplies both a measurement of the noise between bursts and of the signal power. When the RSSIVAL signal goes high, and the RSSI type signal is high, then a valid signal power measurement is available on the RSSI bus. When the RSSIVAL signal goes high, and the RSSI type signal is low, then a valid noise power measurement is available on the
RSSI bus. RSSIVAL goes high in relation to the Signal/Noise Accumulator completing a measurement, as shown in the timing diagram, Figure 5. The input signal is temperature compensated and the analog supply has local regulation in order to make the RSSI measurement accurate to within 2 dB, typical, over a 0 to 70C range. Use RSSI output signal strength look-up tables 1 and 2 to convert the RSSI number (in Hex) to a power reading.
I/O Signal Description
5.1 J3 40 pin straight header connector, SAMTEC TLW-120-06-6-D (suggested mating connector: 3M Part #3448-89140 with strain relief (or) Digit Key Part #MKSR40-ND)
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Signal Name +5V +5V +12V GND +12V RxData GND N/C N/C GND Reset N/C N/C N/C GND GND N/C AcqEn
Description Digital Power Digital Power Analog Power Ground Analog Power Serial Data Input for configuring the 9244. Ground Reserved Spare Ground Active high reset. Must be held high for >100us after 9244 is powered up. Spare Spare Spare Ground Ground Reserved Acquisition enable input. (1k pull-up to +5v) Hi = receiver will acquire Low = receiver will not acquire
19
PktLenSel
Packet length select. (1k pull-up to +5v) Hi = packet length "A" Low = packet length "B"
20
N/C
Spare
STEL-9244
7
PRELIMINARY PRODUCT INFORMATION
I/O Signal Description, Cont'd.
5.1 J3, Cont'd.
Pin Number 21 22 23 Signal Name MCLKIN N/C RSSINHOFF Description Master Clock Input, 43.52 MHz, TTL level (future) Spare RSSI noise measurement holdoff input. (1k pull-down to ground) Hi = RSSI noise measurements disabled. Low = RSSI noise measurements enabled. 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DataOut DataVal RSSI TYPE ClkOut RSSIVAL RSSIEN N/C GatedClk RSSI7 RSSI6 RSSI5 RSSI4 RSSI3 RSSI2 RSSI1 RSSI0 N/C Demodulated data output at 2.56 Mbps. Data Valid output. Frames entire data packet. Active high. Hi = signal measurement; Low = noise measurement Recovered clock output. Rises at the center of each demodulated data bit. Runs continuously. Rising edge occurs when RSSI data & RSSI Type change to new state. Pulse width = 1 symbol Enables the RSSI lines to drive out. Active low input. Spare Gated clock output. Same as ClkOut above, except that it is enabled by DataVal, and is thus not continuously running. Received Signal Strength Indicator (msb) Received Signal Strength Indicator Received Signal Strength Indicator Received Signal Strength Indicator Received Signal Strength Indicator Received Signal Strength Indicator Received Signal Strength Indicator Received Signal Strength Indicator (lsb) Spare
Power-on Configuration
After power is applied to the board, the Reset input must be asserted. After the Reset is released, the board requires approximately 10 seconds to configure itself for operation.
PRELIMINARY PRODUCT INFORMATION
8
STEL-9244
STEL 9244 Burst Demodulator Added Features as of 10/9/96
1. Dual Packet Length Control The packet length of the received burst is selectable between two values by an external TTL signal, called Packet Length Select, applied to pin 19 of connector J3. A high input will select packet length "A" and a low input will select packet length "B." Packet lengths "A" and "B" are specified by downloading a command via the serial interface. The format for these commands is described on page 6. Packet length "A" is specified in bytes #4 and #5, and packet length "B" is specified in bytes #16 and #17. The packet lengths can be programmed for up to 64K symbols. If no signal is applied to pin 19, the default is packet length "A." 2. External Acquisition Enable An external TTL signal, called Acquisition Enable, applied to pin 18 of connector J3 will control whether or not the receiver will attempt to acquire. A high input will allow the receiver to acquire and a low input will disable all acquisition functions. If no signal is applied the default state allows acquisition. When the acquisition is disabled, the noise RSSI function is still enabled and output measurements will continue as normal. 3. Noise RSSI Measurement Hold Off Pin This feature enables synchronization of the noise RSSI measurements with packet length boundaries via a control pin. An external TTL signal, called Noise RSSI Hold Off, applied to pin 23 of connector J3 controls when noise RSSI measurements are taken and output. If this signal is low, noise RSSI measurements are enabled, when it is high, noise RSSI measurements are disabled. This control signal is sampled on the rising edge of an internal version of RSSI Valid. Therefore, if Noise RSSI Hold Off is asserted after RSSI Valid goes high to indicate a completed signal measurement, one noise RSSI measurement will be performed, and then the circuit will be disabled untill Noise RSSI Hold Off is deasserted. If no signal is connected to this pin, the default is that noise RSSI measurements will be enabled. 4. Noise RSSI Measurement Hold Off Register This enables synchronization of the Noise RSSI measurements with packet length boundaries via a programmable counter value. After the end of a burst, a Noise RSSI measurement will be taken. Subsequent Noise RSSI measurements will then be held off until after the programmed number of symbol periods has passed. This delay can be programmed by downloading a command via the serial interface. It is specified in bytes #19 and #20, and can be programmed for zero to 64K - 1 symbols periods. If a data burst comes along before the delay has elapsed, then a Signal RSSI measurement and a subsequent Noise RSSI measurement will be performed, and then the hold off count will start from the beginning. The default hold off delay is zero symbols. 5. Unique Word Detect to Qualify Acquisition A circuit has been added to qualify the acquisition process and therefore reduce false detects. The circuit looks for the string of zeroes that is present at the end of the packet's preamble. When the receiver gets a signal detection, it will either continue the acquisition process or cancel it, depending on whether the string of zeroes has been found. The number of zeroes in the preamble is fourteen, and the number of zeroes that the circuit searches for is programmable from zero to fourteen via the serial interface using byte #18. The default match value is 12.
STEL-9244
9
PRELIMINARY PRODUCT INFORMATION
RSSI Output Signal Strength Look-up Table Signal
Signal RSSI Value (Hex)
11 12 15 18 1B 1E 22 26 2B 2F 36 3D 45 4D 58 61 6D 79 89 95 AA BC C9 D2 DA DE E2 E6
Noise
Absolute** Power (dBm) (BW= 1.28 MHz)
-55.10 -54.48 -53.31 -52.29 -51.46 -50.41 -49.40 -48.42 -47.42 -46.39 -45.40 -44.39 -43.32 -42.36 -41.35 -40.36 -39.34 -38.36 -37.35 -36.35 -35.37 -34.38 -33.36 -32.35 -31.28 -30.38 -29.46 -28.46
Typical* Absolute** Standard Power Deviation (dBmV) (LSB)
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.5 1.5 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 2.0 -6.35 -5.73 -4.56 -3.54 -2.71 -1.66 -0.65 0.33 1.33 2.36 3.35 4.36 5.43 6.39 7.40 8.39 9.41 10.39 11.40 12.40 13.38 14.37 15.40 16.40 17.47 18.37 19.29 20.40
Signal RSSI Value (Hex)
22 26 2A 30 37 3E 46 4F 5A 63 73 82 93 A6 BF
Typical* Absolute** Standard Power Deviation (dBmV) (LSB)
2.0 2.0 2.0 2.5 2.5 3.0 3.0 3.5 4.0 4.5 6.0 7.0 8.0 10.0 12.0 -21.40 -20.37 -19.43 -18.35 -17.36 -16.30 -15.33 -14.34 -13.32 -12.36 -11.33 -10.35 -9.38 -8.37 -7.37
Absolute** Power (dBm) (BW= 1.28 MHz)
-70.15 -69.12 -68.18 -67.10 -66.11 -65.05 -64.08 -63.09 -62.07 -61.11 -60.09 --59.10 -58.13 -57.12 -56.12
Table 1 * Expected variation in RSSI measurement. ** 75 ohm system
Table 2
PRELIMINARY PRODUCT INFORMATION
10
STEL-9244
Data Timing
PREAMBLE Tx RF 111 00 1 0 0000000
DATA
25-1/2 SYMBOL PERIODS* 27 SYMBOL PERIODS*
DATA DEMODULATED DATA OUTPUT 60 ns DATA VALID
90 ns
CLOCK OUT 140 ns
GATED CLOCK
* Approximate. Actual delay may be as much as one symbol period less.
WCP 51549.c-11/22/96
Figure 4
RSSI Timing Diagram
RF INPUT
PR
DATA BURST 1
PR
DATA BURST 2
PR
DATA BURST 3
DATA VALID RSSI ACCUMULATOR CONTENTS
MEAS
M1* SYMBOLS
M2* SYMBOLS
NOISE 0 (ABORTED)
SIGNAL 1
RSSI
NOISE 1 (ABORTED) 1 SYMBOL
SIGNAL 2
NOISE 2 2 SYMBOLS
NOISE 3
NOISE 4 (INVALID)
SIGNAL 3
NOISE 5 (ABORTED)
NOISE 6
24 SYMBOLS
RSSI VALID
SIGNAL 1 SIGNAL 2 NOISE 2 NOISE 3 22 SYMBOLS SIGNAL 3
RSSI TYPE
2 SYMBOLS SIGNAL 1 SIGNAL 2 NOISE 2 NOISE 3 SIGNAL 3
RSSI DATA
*MI: Signal Accumulator Length, M2 = Noise Accumulator Length Note: RSSI VALID pulse can be used to latch-in RSSI DATA and/or RSSI TYPE for the reporting of RSSI signal strength
WCP 51550.c-8/16/96
Figure 5 STEL-9244 11 PRELIMINARY PRODUCT INFORMATION
DATA VALID tps PACKET LENGTH SELECT tph tas ACQUISITION ENABLE tah
RSSI VALID tns tnh NOISE RSSI* HOLDOFF
* Noise RSSI Holdoff is recognized at the rising edge of an earlier version of RSSI VALID. Symbol tps tph tas tah tns tnh Parameter Packet Length Select Setup Time Packet Length Select Hold Time Acquisition Enable Setup Time Acquisition Enable Hold Time Noise RSSI Holdoff Setup Time Noise RSSI Holdoff Hold Time Min 5s 0s 23s 0s 22s 0s
WCP 52488.c-11/22/96
Figure 6
PRELIMINARY PRODUCT INFORMATION
12
STEL-9244
STEL-9244 Test Fixture
4.7k 3 9 Pin "D" Female 5
74HC04 J3-6 UART Serial Data Input to 9244
6.2k
Data Out J3-24 (Same as J4-4 on 9244 Silkscreen) J3-31 Gated Clk (Same as J4-11 on 9244 Silkscreen)
To Bit Error Rate Tester
+5v
Reset J3-11 100
WCP 51753B.c-9/06/96
Figure 7 - Test Fixture
STEL-9244
13
PRELIMINARY PRODUCT INFORMATION
Mechanical
0.30 0.00 0.20
5.075 5.25 0.00 0.20 Test (Not Loaded) 0.55 0.875
RF In 1.575 SMB (Male) .30 High
C46
C46
Header .40 High Digital I/O, and Power
3.20
0.12 (x4) Hole, 0.25 (x4) Pad 4.30 4.50 Silkscreen Top 0.20 0.00
Dimensions In Inches Not to Scale Component Height (other than as noted) Top Side: 0.25 inches Bottom Side: 0.1 inches Board Thickness: 0.064 inches
5.30 5.50
WCP 51499.c-9/06/96
Figure 8 - Board Mechanical
------------------------------------------------------------------------
PRELIMINARY PRODUCT INFORMATION
14
STEL-9244
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied Intel may make changes to specifications and product descriptions at any time, without notice.
warranty, relating to sale and/or use of Intel(R) products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.
For Further Information Call or Write
INTEL CORPORATION Cable Network Operation 350 E. Plumeria Drive, San Jose, CA 95134 Customer Service Telephone: (408) 545-9700 Technical Support Telephone: (408) 545-9799 FAX: (408) 545-9888
Copyright (c) Intel Corporation, December 15, 1999. All rights reserved

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